Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformityopen access
- Authors
- Kim, Taikyu; Choi, Cheol Hee; Byeon, Pilgyu; Lee, Miso; Song, Aeran; Chung, Kwun-Bum; Han, Seungwu; Chung, Sung-Yoon; Park, Kwon-Shik; Jeong, Jae Kyeong
- Issue Date
- Jan-2022
- Publisher
- NATURE RESEARCH
- Citation
- NPJ 2D MATERIALS AND APPLICATIONS, v.6, no.1, pp.1 - 7
- Indexed
- SCIE
SCOPUS
- Journal Title
- NPJ 2D MATERIALS AND APPLICATIONS
- Volume
- 6
- Number
- 1
- Start Page
- 1
- End Page
- 7
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/139821
- DOI
- 10.1038/s41699-021-00280-7
- ISSN
- 2397-7132
- Abstract
- Achieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm(2) V-1 s(-1) and an I-ON/OFF ratio of 5.8 x 10(5) with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of similar to 75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.
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