A 320-MS/s 2-b/cycle Second-order Noise-shaping SAR ADC

Abstract

—A 2nd-order Noise-Shaping ADC using a 2-bit/cycle SAR ADC is proposed. With a designated reference DAC and a signal DAC, three comparators in the SAR ADC enable 2-bit conversion in each comparison cycle. The noise transfer function (NTF) of the ADC is implemented in an error-feedback structure to bypass the need for power-consuming integrator. A low-gain switched input/output open-loop residue amplifier and a switched-capacitor FIR filter realizes the NTF coefficients. The proposed ADC was designed with a 28-nm CMOS process with 1-V power supply. The SPICE simulation results show that the designed ADC has SNDR of 69.9 dB and power consumption of 4.08 mW, when operated with a sampling rate of 320-MS/s and OSR of 8 achieving a Walden figure-of-merit (FoM) of 39.9-fJ/conv.-step.