A SCAN Chain Generator for Verification of Full-Custom Integrated Circuits

Abstract

This paper demonstrates a circuit generator that produces schematic and layout of custom-digital SCAN chains for design-for-Test (DFT) of analog and mixed-signal integrated circuits. The schematic/layout generator scrips are parameterized to cover various test cases; the number of bits and their pin names, aspect ratio, and buffer sizes can be configured by users. Various instances are generated in a 40-nm CMOS technology to verify the generator's capability to produce parameterized and DRC-clean layouts.