A SCAN Chain Generator for Verification of Full-Custom Integrated Circuits
- Authors
- Shin, Taeho; Han, Jae duk
- Issue Date
- Nov-2021
- Publisher
- IEEE
- Keywords
- design automation; design for test; full-custom digital circuit; scan-based testing
- Citation
- Proceedings - International SoC Design Conference 2021, ISOCC 2021, pp.335 - 336
- Indexed
- SCOPUS
- Journal Title
- Proceedings - International SoC Design Conference 2021, ISOCC 2021
- Start Page
- 335
- End Page
- 336
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/140377
- DOI
- 10.1109/ISOCC53507.2021.9613981
- ISSN
- 2163-9612
- Abstract
- This paper demonstrates a circuit generator that produces schematic and layout of custom-digital SCAN chains for design-for-Test (DFT) of analog and mixed-signal integrated circuits. The schematic/layout generator scrips are parameterized to cover various test cases; the number of bits and their pin names, aspect ratio, and buffer sizes can be configured by users. Various instances are generated in a 40-nm CMOS technology to verify the generator's capability to produce parameterized and DRC-clean layouts.
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