Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology
- Authors
- Park, Heechun; Chang, Kyungjoon; Jeong, Jooyeon; Ahn, Jaehoon; Chung, Ki-Seok; KIM, Taewhan
- Issue Date
- Nov-2021
- Publisher
- IEEE
- Citation
- Proceedings - International SoC Design Conference 2021, ISOCC 2021, pp.215 - 218
- Indexed
- SCOPUS
- Journal Title
- Proceedings - International SoC Design Conference 2021, ISOCC 2021
- Start Page
- 215
- End Page
- 218
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/140378
- DOI
- 10.1109/ISOCC53507.2021.9614026
- ISSN
- 2163-9612
- Abstract
- Design-Technology-co-optimization (DTCO) is essential in deep submicron technologies (e.g., 14nm and below) to co-optimize process technology and design rules and obtain more benefit from advanced node. As the process technology shrinks to deep submicron, the importance of back-end-of-line (BEOL) interconnect in a full chip design drastically grows since its less-Than-micron width brings unexpected critical design rules that requires novel design techniques. In this paper, we provide a comprehensive survey on recent challenging issues and cutting-edge design methodologies for DTCO in deep submicron interconnect technology, which includes: offset assignment for pin accessibility; monolithic 3D integration; middle-of-line (MOL) utilization for routing; BEOL-Aware representative critical path circuit synthesis; and buried power rail (BPR).
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