Effect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories
- Authors
- Lee, Jun Gyu; Jung, Woo Je; Park, Jae Hyeon; Yoo, Keon-Ho; Kim, Tae Whan
- Issue Date
- Sep-2021
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Flash memories; Logic gates; Electron traps; Threshold voltage; Tools; Programming; Licenses; 3-D NAND flash memories; threshold voltage shift; tapered channel
- Citation
- IEEE Journal of the Electron Devices Society, v.9, pp.774 - 777
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Journal of the Electron Devices Society
- Volume
- 9
- Start Page
- 774
- End Page
- 777
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/141132
- DOI
- 10.1109/JEDS.2021.3104843
- ISSN
- 2168-6734
- Abstract
- The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (V-T), between the upper and the lower cells. We simulated the tapered channel effect by using Sentaurus technology, computer-aided design (TCAD) tools, and based on the results, we propose a novel method to lessen the non-uniformity of the threshold voltage shift (Delta V-T) between the cells. The difference in Delta V-T between the upper and the lower cells due to the tapered channel can be reduced by employing a tapered blocking oxide layer with a proper taper angle. These results will be helpful in designing reliable 3-D NAND flash memories.
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