Speed Enhancement of WSi2 Nanocrystal Memory with Barrier-Engineered Si3N4/HfAlO Tunnel Layer
- Authors
- Lee, Dong Uk; Lee, Hyo Jun; Kim, Eun Kyu; You, Hee-Wook; Cho, Won-Ju
- Issue Date
- Jun-2012
- Publisher
- IOP PUBLISHING LTD
- Citation
- JAPANESE JOURNAL OF APPLIED PHYSICS, v.51, no.6, pp.1 - 5
- Indexed
- SCIE
SCOPUS
- Journal Title
- JAPANESE JOURNAL OF APPLIED PHYSICS
- Volume
- 51
- Number
- 6
- Start Page
- 1
- End Page
- 5
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/144760
- DOI
- 10.1143/JJAP.51.06FE13
- ISSN
- 0021-4922
- Abstract
- WSi2 nanocrystal nanofloating gate capacitors with multistacked Si3N4/HfAlO high-k tunnel layers were fabricated and their electrical properties were characterized. The thicknesses of the Si3N4 and HfAlO tunnel layers were 1.5 and 3 nm, respectively. The asymmetrical Si3N4/HfAlO tunnel layer was modulated to enhance the tunneling efficiency to improve program and erase speeds. The flat-band voltage shift of the WSi2 nanofloating gate capacitor was about 7.2 V after applied voltages swept were from -10 to 10 V and from 10 to -10 V. Then, the program/erase speeds and the memory window under programming and erasing at +/- 7 V were 300 mu s and 1 V, respectively. As demonstrated in the results, the WSi2 nanocrystal memory with barrier-engineered Si3N4/HfAlO layers could be applied to enhance the program and erase speeds at low operating voltages for nanocrystal nonvolatile memory application.
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