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A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET

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dc.contributor.authorWang, Angie-
dc.contributor.authorBae, Woorham-
dc.contributor.authorHan, Jae duk-
dc.contributor.authorBailey, Stevo-
dc.contributor.authorOcal, Orhan-
dc.contributor.authorRigge, Paul-
dc.contributor.authorWang, Zhongkai-
dc.contributor.authorRamchandran, Kannan-
dc.contributor.authorAlon, Elad-
dc.contributor.authorNikolic, Borivoje-
dc.date.accessioned2022-07-09T11:54:59Z-
dc.date.available2022-07-09T11:54:59Z-
dc.date.created2021-05-14-
dc.date.issued2019-07-
dc.identifier.issn0018-9200-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/147410-
dc.description.abstractA 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three sets of 25x, 27x, and 32x sub-sampling successive approximation register (SAR) ADCs acquire signal with similar to 5.4-6.3 effective number of bits (ENOB)/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point fast Fourier transforms (FFTs), a signal location estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order, fifth-generation reduced instruction set (RISC-V) Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8 mW with a 3.78-GHz reference clock. At 400 MHz and 0.7-V digital supply voltage (VDD), the Rocket core and the FFAST digital signal processing (DSP) together consume 133.5 mW.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET-
dc.typeArticle-
dc.contributor.affiliatedAuthorHan, Jae duk-
dc.identifier.doi10.1109/JSSC.2019.2913099-
dc.identifier.scopusid2-s2.0-85068229648-
dc.identifier.wosid000473434300017-
dc.identifier.bibliographicCitationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.7, pp.1993 - 2008-
dc.relation.isPartOfIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.citation.titleIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.citation.volume54-
dc.citation.number7-
dc.citation.startPage1993-
dc.citation.endPage2008-
dc.type.rimsART-
dc.type.docType정기학술지(Article(Perspective Article포함))-
dc.description.journalClass1-
dc.description.isOpenAccessY-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusINTERLEAVED ADC-
dc.subject.keywordPlusGHZ-
dc.subject.keywordAuthorAnalog-to-digital converters (ADCs)-
dc.subject.keywordAuthorBerkeley Analog Generator (BAG)-
dc.subject.keywordAuthorConstructing Hardware in a Scala Embedded Language (Chisel)-
dc.subject.keywordAuthorfast Fourier transform (FFT)-
dc.subject.keywordAuthorhardware generators-
dc.subject.keywordAuthorfifth-generation reduced instruction set computer (RISC-V)-
dc.subject.keywordAuthorspectrum sensing-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8738896-
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