A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET
DC Field | Value | Language |
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dc.contributor.author | Wang, Angie | - |
dc.contributor.author | Bae, Woorham | - |
dc.contributor.author | Han, Jae duk | - |
dc.contributor.author | Bailey, Stevo | - |
dc.contributor.author | Ocal, Orhan | - |
dc.contributor.author | Rigge, Paul | - |
dc.contributor.author | Wang, Zhongkai | - |
dc.contributor.author | Ramchandran, Kannan | - |
dc.contributor.author | Alon, Elad | - |
dc.contributor.author | Nikolic, Borivoje | - |
dc.date.accessioned | 2022-07-09T11:54:59Z | - |
dc.date.available | 2022-07-09T11:54:59Z | - |
dc.date.created | 2021-05-14 | - |
dc.date.issued | 2019-07 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/147410 | - |
dc.description.abstract | A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three sets of 25x, 27x, and 32x sub-sampling successive approximation register (SAR) ADCs acquire signal with similar to 5.4-6.3 effective number of bits (ENOB)/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point fast Fourier transforms (FFTs), a signal location estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order, fifth-generation reduced instruction set (RISC-V) Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8 mW with a 3.78-GHz reference clock. At 400 MHz and 0.7-V digital supply voltage (VDD), the Rocket core and the FFAST digital signal processing (DSP) together consume 133.5 mW. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Han, Jae duk | - |
dc.identifier.doi | 10.1109/JSSC.2019.2913099 | - |
dc.identifier.scopusid | 2-s2.0-85068229648 | - |
dc.identifier.wosid | 000473434300017 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.7, pp.1993 - 2008 | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 54 | - |
dc.citation.number | 7 | - |
dc.citation.startPage | 1993 | - |
dc.citation.endPage | 2008 | - |
dc.type.rims | ART | - |
dc.type.docType | 정기학술지(Article(Perspective Article포함)) | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | INTERLEAVED ADC | - |
dc.subject.keywordPlus | GHZ | - |
dc.subject.keywordAuthor | Analog-to-digital converters (ADCs) | - |
dc.subject.keywordAuthor | Berkeley Analog Generator (BAG) | - |
dc.subject.keywordAuthor | Constructing Hardware in a Scala Embedded Language (Chisel) | - |
dc.subject.keywordAuthor | fast Fourier transform (FFT) | - |
dc.subject.keywordAuthor | hardware generators | - |
dc.subject.keywordAuthor | fifth-generation reduced instruction set computer (RISC-V) | - |
dc.subject.keywordAuthor | spectrum sensing | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8738896 | - |
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