GATE: A generalized dataflow-level approximation tuning engine for data parallel architectures
- Authors
- Kang, Seokwon .; Yu, Yongseung; Kim, Jiho; Park, Yongjun
- Issue Date
- Jun-2019
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Citation
- Proceedings - Design Automation Conference, pp.1 - 6
- Indexed
- SCOPUS
- Journal Title
- Proceedings - Design Automation Conference
- Start Page
- 1
- End Page
- 6
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/147627
- DOI
- 10.1145/3316781.3317833
- ISSN
- 0738-100X
- Abstract
- Although approximate computing is widely used, it requires substantial programming effort to find appropriate approximation patterns among multiple pre-defined patterns to achieve a high performance. Therefore, we propose an automatic approximation framework called GATE to uncover hidden opportunities from any data-parallel program regardless of the code pattern or application characteristics using two compiler techniques, namely subgraph-level approximation (SGLA) and approximate thread merge(ATM). GATE also features conservative/aggressive tuning and dynamic calibration to maximize the performance while maintaining the TOQ level during runtime. Our framework achieves an average performance gain of 2.54x over the baseline with minimum accuracy loss.
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