Optimal Checkpoint Selection with Dual-Modular Redundancy Hardening
- Authors
- Kang, Shin-Haeng; Park, Hae-woo; Kim, Sungchan; Oh, Hyunok; Ha, Soonhoi
- Issue Date
- Jul-2015
- Publisher
- IEEE COMPUTER SOC
- Keywords
- Checkpoint; task graph; multiprocessor; reliability; optimal algorithm
- Citation
- IEEE TRANSACTIONS ON COMPUTERS, v.64, no.7, pp.2036 - 2048
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON COMPUTERS
- Volume
- 64
- Number
- 7
- Start Page
- 2036
- End Page
- 2048
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/156842
- DOI
- 10.1109/TC.2014.2349492
- ISSN
- 0018-9340
- Abstract
- With the continuous scaling of semiconductor technology, failure rate is increasing significantly so that reliability becomes an important issue in multiprocessor system-on-chip (MPSoC) design. We propose an optimal checkpoint selection with task duplication hardening to tolerate transient faults. A target application is specified in a task graph, and the schedule/checkpoint placements are determined at design time. The proposed optimal algorithm minimizes the checkpoint overhead with a latency constraint. Experimental results show that the proposed algorithm effectively reduces the minimum end-to-end latency to perform a fault-tolerant schedule. In addition, the proposed algorithm dramatically decreases the checkpointing overhead on uniprocessor and multiprocessor systems compared with a greedy approach and an equidistant algorithm.
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