Dynamic power management for embedded processors in system-on-chip designs

Abstract

Dynamic power management (DPM), which exploits low-power states of the target device, has been a key research issue to overcome the limited battery life of mobile devices. For efficient power management, today's power management unit in a system-on-chip for mobile devices supports multiple low-power states for embedded processors. Unfortunately, the DPM policies implemented in modern operating systems are not appropriate for processors because they may not understand the idleness of the processor accurately. There may be significant performance degradation if the DPM policy module misunderstands that the processor is idle even when there are many interrupt requests to handle. A novel DPM scheme for embedded processors considering the system response time as well as power reduction is proposed. Experimental results show that the proposed DPM policy achieves performance improvement by up to 25% compared to a conventional DPM policy with a similar amount of power reduction.