Fabrication of on-chip fluidic channels incorporating nanopores using self-aligned double layer resist processing technique

Abstract

The authors report on the development of a self-aligned double layer resist processing technique that allows incorporation of ion channel nanopores into on-chip microfluidic channels. The patterned positive/negative electron-beam resist double layer acts as a sacrificial template for the fabrication of on-chip fluidic channels and the nanopores. By controlling the resist dimensions, it was possible to tailor the shape of the on-chip fluidic channel and the nanopore dimensions. Using this technique, the authors demonstrated the fabrication of sub-10 nm nanopore arrays on 2 mu m wide and 800nm high on-chip fluidic channels. With further developments, it will be possible to have controllable on-chip nanopores with integrated nanofluidics.