Modified wirte-and-verify scheme for improving the endurance of multi-level cell phase-change memory using Ge-doped SbTe
- Authors
- Zhang, Gang; Wu, Zhe; Jeong, Jeung-hyun; Jeong, Doo Seok; Yoo, Won Jong; Cheong, Byung-ki
- Issue Date
- Oct-2012
- Publisher
- PERGAMON-ELSEVIER SCIENCE LTD
- Keywords
- Modified WAV scheme; Endurance improvement; Phase-change memory
- Citation
- SOLID-STATE ELECTRONICS, v.76, pp.67 - 70
- Indexed
- SCIE
SCOPUS
- Journal Title
- SOLID-STATE ELECTRONICS
- Volume
- 76
- Start Page
- 67
- End Page
- 70
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/164468
- DOI
- 10.1016/j.sse.2012.06.003
- ISSN
- 0038-1101
- Abstract
- In this study, a modified write-and-verify (WAV) scheme is proposed for improving the programming/erasing (P/E) endurance of multi-level cell (MLC) phase-change memory (PCM) using Ge-doped SbTe (GeST). A dual reference data read method is developed to detect the level margin decay during P/E cycling, and a trigger condition is designed to trigger self-repair for the degraded cells before any P/E error for the modified WAV scheme. Experimental results suggest that the modified WAV scheme effectively extends the P/E endurance of PCM using GeST during 4-level P/E by at least 10 times. The modified WAV scheme is expected to improve the endurance of MLC-PCM of system applications.
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