Plasma atomic layer deposited TiN metal gate for three dimensional device applications: Deposition temperature, capping metal and post annealing
- Authors
- Heo, Seung Chan; Choi, Changhwan
- Issue Date
- Jun-2012
- Publisher
- ELSEVIER
- Keywords
- Plasma atomic layer deposition; Flatband voltage (V-FB); Mid-gap work-function; 3-D device
- Citation
- MICROELECTRONIC ENGINEERING, v.94, pp.11 - 13
- Indexed
- SCIE
SCOPUS
- Journal Title
- MICROELECTRONIC ENGINEERING
- Volume
- 94
- Start Page
- 11
- End Page
- 13
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/165391
- DOI
- 10.1016/j.mee.2011.12.001
- ISSN
- 0167-9317
- Abstract
- We evaluated plasma atomic layer deposition (ALD)-based TiN as a gate electrode for the metal-oxide-semiconductor (MOS) devices application by varying thickness, deposition temperature, subsequent metal capping layer and post forming gas anneal (FGA). Lower deposition temperature, thinner TiN, in situ processed ALD TaN capping provides more positive flatband voltage (V-FB), compatible for p-type MOS devices. Equivalent oxide thickness (EOT) can be scaled down to similar to 1.2 nm range. With post 450 degrees C FGA, additional negative V-FB shift is observed while EOT is substantially increased (>0.2-0.3 nm). Mid-gap work-function behavior is observed with plasma ALD-based TiN, indicating a strong potential candidate metal gate material for replacement gate processed three-dimensional (3-D) devices such as FiN shaped field effect transistor (FiNFET).
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