Reduced Distribution of Threshold Voltage Shift in Double Layer NiSi2 Nanocrystals for Nano-Floating Gate Memory Applications
- Authors
- Choi, Sungjin; Lee, Junhyuk; Kim, Donghyoun; Oh, Seulki; Song, Wangyu; Choi, Seonjun; Choi, Eunsuk; Lee, Seung-Beck
- Issue Date
- Dec-2011
- Publisher
- AMER SCIENTIFIC PUBLISHERS
- Keywords
- Nano Floating Gate Memory; NiSi2; Nanocrystals; Double Layer
- Citation
- JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v.11, no.12, pp.10553 - 10556
- Indexed
- SCIE
SCOPUS
- Journal Title
- JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY
- Volume
- 11
- Number
- 12
- Start Page
- 10553
- End Page
- 10556
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/166986
- DOI
- 10.1166/jnn.2011.4009
- ISSN
- 1533-4880
- Abstract
- We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/-2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.
- Files in This Item
-
Go to Link
- Appears in
Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
![qrcode](https://api.qrserver.com/v1/create-qr-code/?size=55x55&data=https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/166986)
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.