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다중화된 곱셈기로 구현된 델타-시그마 A/D 컨버터용 데시메이션 필터Multiplier Optimized Implementation of Decimation Filter for Delta-Sigma ADC
- Other Titles
- Multiplier Optimized Implementation of Decimation Filter for Delta-Sigma ADC
- Issue Date
- Nov-2011
- Publisher
- 대한전자공학회
- Citation
- 2011년 대한전자공학회 추계학술대회 논문집, no. , pp.89 - 90
- Indexed
- OTHER
- Journal Title
- 2011년 대한전자공학회 추계학술대회 논문집
- Start Page
- 89
- End Page
- 90
- Abstract
- An e conomical implementation method of multi-rate multi-stage decimation filter is presented. The filter is composed of a CIC filter stage, which decimates large data rate without any multipliers, and cascaded half-band filter stages with optimized multipliers usage. This filter was successfully applied to the decimation of delta-sigma modulator output.
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Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
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Related Researcher
- Park, Sang Gyu
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)