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정착시간과 레귤레이션 특성을 개선한 LDO(Low Dropout Regulator)의 설계A Design of LDO(Low Dropout Regulator) with Enhanced Settling Time and Regulation Property
- Other Titles
- A Design of LDO(Low Dropout Regulator) with Enhanced Settling Time and Regulation Property
- Issue Date
- Sep-2011
- Publisher
- 대한전기학회
- Keywords
- LDO; Line Regulation; Load Regulation; Reference Source; Settling Time
- Citation
- 전기학회 논문지 P권, v.60, no.3, pp.126 - 132
- Indexed
- KCI
- Journal Title
- 전기학회 논문지 P권
- Volume
- 60
- Number
- 3
- Start Page
- 126
- End Page
- 132
- ISSN
- 1229-800x
- Abstract
- A conventional LDO(Low Dropout Regulator) uses one OPAMP and one signal path. This means that OPAMP's DC Gain and Bandwidth can't optimize simultaneously within usable power. This also appears that regulation property and settling time of LDO can't improve at the same time. Based on this idea, a proposed LDO uses two OPAMP and has two signal path. To improve regulation property, OPAMP where is used in the path which qualities DC gain on a large scale, bandwidth designed narrowly. To improve settling time, OPAMP where is used in the path which qualities DC gain small, bandwidth designed widely. A designed LDO used 0.5um 1P2M process and provided 200mA of output current. A line regulation and load regulation is 12.6mV/V, 0.25mV/mA, respectively. And measured settling time is 1.5us in 5V supply voltage.
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Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
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Related Researcher
- Park, Jea Gun
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)