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Low-Power Design of Hardware One-Time Password Generators for Card-Type OTPs

Authors
Lee, Sung-JaeLee, Jae SeongLee, Mun-KyuLee, Sang JinChoi, Doo-HoKim, Dong Kyue
Issue Date
Aug-2011
Publisher
WILEY
Keywords
One-time password; AES; HMAC; card-type OTP; low-power hardware implementation
Citation
ETRI JOURNAL, v.33, no.4, pp.611 - 620
Indexed
SCIE
SCOPUS
KCI
Journal Title
ETRI JOURNAL
Volume
33
Number
4
Start Page
611
End Page
620
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/167845
DOI
10.4218/etrij.11.0110.0392
ISSN
1225-6463
Abstract
Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. En this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the Sub Bytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.
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COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)
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