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Efficiency optimization of charge pump circuit in NAND FLASH memory
- Issue Date
- Aug-2011
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- NAND FLASH; charge pump; efficiency; current reduction
- Citation
- IEICE ELECTRONICS EXPRESS, v.8, no.16, pp.1343 - 1347
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 8
- Number
- 16
- Start Page
- 1343
- End Page
- 1347
- ISSN
- 1349-2543
- Abstract
- In this paper, power efficiency optimization scheme of charge pump circuit in NAND FLASH memory was proposed. The proposed scheme was implemented in program/erase charge pump by pump stage number control method. The maximum power efficiency of this pump is about 30%, and the maximum point is around 70% point of highest voltage level. So in this paper, to operate program/erase pump in highest power efficiency area, the pump stage number control scheme is proposed and evaluated in 20nm 64Gb MLC NAND FLASH memory circuit. Simulation result shows overall improvement of power efficiency, and at the wafer test about 10mA peak current reduction and overall improvement of power dissipation are found.
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Related Researcher
- Park, Jea Gun
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)