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A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit

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dc.contributor.authorSutardja, Nicholas-
dc.contributor.authorHan, Jaeduk-
dc.contributor.authorNarevsky, Nathan-
dc.contributor.authorAlon, Elad-
dc.date.accessioned2021-07-30T04:51:54Z-
dc.date.available2021-07-30T04:51:54Z-
dc.date.created2021-05-14-
dc.date.issued2020-11-
dc.identifier.issn1930-8833-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/1695-
dc.description.abstractThis paper presents a 28nm CMOS 1-20Gb/s energy proportional transmitter with 2-tap DDR SC FFE, 64:2 1-latch MUX serialization, rapid-on/off LC OSC, and adjustable clock divider. Switched Capacitor frontend allows for fully dynamic operation for minimal quiescent current consumption. Fast startup time is achieved through the 1-latch based MUX SER along with the on/off LC OSC and the adjustable clock divider. The transmitter operates from 1-20Gb/s, occupies 0.19mm 2 , and consumes 0.72-0.62 pJ/bit.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-
dc.titleA 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit-
dc.typeArticle-
dc.contributor.affiliatedAuthorHan, Jaeduk-
dc.identifier.doi10.1109/ESSCIRC.2019.8902684-
dc.identifier.bibliographicCitationIEEE 45th European Solid State Circuits Conference (ESSCIRC), pp.273 - 276-
dc.relation.isPartOfIEEE 45th European Solid State Circuits Conference (ESSCIRC)-
dc.citation.titleIEEE 45th European Solid State Circuits Conference (ESSCIRC)-
dc.citation.startPage273-
dc.citation.endPage276-
dc.type.rimsART-
dc.type.docTypeProceeding-
dc.description.journalClass3-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassother-
dc.subject.keywordAuthorTransmitter-
dc.subject.keywordAuthorFFE-
dc.subject.keywordAuthorDDR-
dc.subject.keywordAuthorSwitched Capacitor-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8902684-
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