A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit
- Authors
- Sutardja, Nicholas; Han, Jaeduk; Narevsky, Nathan; Alon, Elad
- Issue Date
- Nov-2020
- Publisher
- IEEE
- Keywords
- Transmitter; FFE; DDR; Switched Capacitor
- Citation
- IEEE 45th European Solid State Circuits Conference (ESSCIRC), pp.273 - 276
- Indexed
- OTHER
- Journal Title
- IEEE 45th European Solid State Circuits Conference (ESSCIRC)
- Start Page
- 273
- End Page
- 276
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/1695
- DOI
- 10.1109/ESSCIRC.2019.8902684
- ISSN
- 1930-8833
- Abstract
- This paper presents a 28nm CMOS 1-20Gb/s energy proportional transmitter with 2-tap DDR SC FFE, 64:2 1-latch MUX serialization, rapid-on/off LC OSC, and adjustable clock divider. Switched Capacitor frontend allows for fully dynamic operation for minimal quiescent current consumption. Fast startup time is achieved through the 1-latch based MUX SER along with the on/off LC OSC and the adjustable clock divider. The transmitter operates from 1-20Gb/s, occupies 0.19mm 2 , and consumes 0.72-0.62 pJ/bit.
- Files in This Item
-
Go to Link
- Appears in
Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles
![qrcode](https://api.qrserver.com/v1/create-qr-code/?size=55x55&data=https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/1695)
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.