Nanoscale surface engineering of a high-kZrO(2)/SiO(2)gate insulator for a high performance ITZO TFTviaplasma-enhanced atomic layer deposition

Abstract

We investigated a high dielectric constant (k) gate insulator (GI) based on the tandem structure of ZrO(2)and SiO(2)to optimize a high performance oxide thin-film transistor (TFT). We analyzed tandem structures with various SiO(2)thicknesses to simultaneously achieve higher ZrO(2)kvalues and better SiO(2)interfacial properties for the In-Sn-Zn-oxide (ITZO) TFT. The TFT exhibited significantly enhanced operational characteristics at a specific SiO(2)thickness compared to the GI structures of only ZrO(2)or SiO2. We determined the mechanism involved in this improvement by adapting various chemical analysis methods. The optimized tandem-structured GI achieved device stability under positive-bias-and-temperature stress test conditions. Consequently, we evaluated the GI optimization criteria for the development of high performance TFTs. We determined the optimized tandem structure properties withkvalue, effective mobility, subthreshold swing, and hysteresis of 17.4, 27.7 cm(2)V(-1)s(-1), 0.17 V dec(-1), and 0.11 V, respectively, for 8 nm SiO(2)on ZrO2.