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Multilevel Dual-Channel NAND Flash Memories with High Read and Program Verifying Speeds Utilizing Asymmetrically-Doped Channel Regions
- Issue Date
- May-2010
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- NAND flash memory; multilevel dual-channel; high-speed multilevel reading; current sensing; high-speed program verifying
- Citation
- IEICE TRANSACTIONS ON ELECTRONICS, v.E93C, no.5, pp.654 - 657
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE TRANSACTIONS ON ELECTRONICS
- Volume
- E93C
- Number
- 5
- Start Page
- 654
- End Page
- 657
- ISSN
- 0916-8524
- Abstract
- The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the highspeed multilevel reading with a wider current sensing margin and the highspeed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed.
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