Capacitor-less memory-cell fabricated on nanoscale unstrained Si layer on strained SiGe layer-on-insulator

Abstract

We investigated the effect of the presence of strained SiGe layer inserted between unstrained Si and buried oxide layer and the Ge concentration in strained SiGe layer on the memory margin of capacitor-less memory-cell. We observed that memory margin of unstrained Si on strained SiGe-on-insulator capacitor-less memory-cells increases with the Ge concentration of the strained SiGe layer and obtained memory margin at the Ge concentration of 19 at% that was 3.2 times larger than that at the silicon-on-insulator capacitor-less memory-cell. This enhancement was due to the potential-barrier lowering increasing exponentially with the Ge concentration resulting from higher hole confinement in spite of the reduction in the saturated drain current.