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Reduced distribution of threshold voltage shift in double layer NiSi 2 nanocrystals for nano-floating gate memory applications
- Authors
- Choi, Sung-Jin; Lee, Jun-Hyuk; Kim, Dong-Hyoun; Oh, Seul-Ki; Song, Wangyu; Choi, Seon-Jun; Lee, Seung-Beck
- Issue Date
- Mar-2010
- Publisher
- IEEE
- Citation
- INEC 2010 - 2010 3rd International Nanoelectronics Conference, Proceedings, pp.1246 - 1247
- Indexed
- SCOPUS
- Journal Title
- INEC 2010 - 2010 3rd International Nanoelectronics Conference, Proceedings
- Start Page
- 1246
- End Page
- 1247
- ISSN
- 0000-0000
- Abstract
- We report on the fabrication and C-V characteristics of double layer NiSi2 nanocrystals (NCs) with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. The variation in threshold voltage shift ΔVTH) was measured for samples at different stress voltages. The ΔVTH increased with applied program voltage from 1.0 V at 3 V to 2.3 V at 7 V. Compared with SiO 2, ΔVTH is reduced to 0.2-0.4 V in each program voltages demonstrating possible multi-level-cell (MLC) operation.
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Related Researcher
- Lee, Seung Beck
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)