Study of layout-effect based on S-parameter extracted by full-wave EM simulation for CMOS RFIC design

Abstract

Layout parasitic components can significantly affect the performance of CMOS RF integrated circuits, and can even make a totally different representation from the circuit designed in schematic. This paper proposes a fast approach to identify the layout effect based on S-parameter of on-chip interconnect structures extracted by 3D full-wave EM simulation. In order to confirm the accuracy of modeled on-chip passive devices used in the approach, S-parameter of interconnections is firstly computed at DC and compared with schematic simulation result. CMOS RF poly-phase filter, as a design example is presented in this paper, where I/Q path mismatch effect and geometric effect are disclosed. Experimental results demonstrate that layout effect can be definitely non-negligible.