Study of layout-effect based on S-parameter extracted by full-wave EM simulation for CMOS RFIC design
- Authors
- Yang, Liu; Choi, Sungju; Kim, Joonchul; Kim, Hyeong dong
- Issue Date
- Dec-2009
- Publisher
- IEEE
- Keywords
- Black-box; CMOS; Electromagnetic; Full wave; Interconnects; On-chip; Poly-phase filter; Quadrature; RFIC; S-parameter
- Citation
- APMC 2009 - Asia Pacific Microwave Conference 2009, pp.2598 - 2601
- Indexed
- SCOPUS
- Journal Title
- APMC 2009 - Asia Pacific Microwave Conference 2009
- Start Page
- 2598
- End Page
- 2601
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/175690
- DOI
- 10.1109/APMC.2009.5385243
- Abstract
- Layout parasitic components can significantly affect the performance of CMOS RF integrated circuits, and can even make a totally different representation from the circuit designed in schematic. This paper proposes a fast approach to identify the layout effect based on S-parameter of on-chip interconnect structures extracted by 3D full-wave EM simulation. In order to confirm the accuracy of modeled on-chip passive devices used in the approach, S-parameter of interconnections is firstly computed at DC and compared with schematic simulation result. CMOS RF poly-phase filter, as a design example is presented in this paper, where I/Q path mismatch effect and geometric effect are disclosed. Experimental results demonstrate that layout effect can be definitely non-negligible.
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