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Low Power MAC Design with Variable Precision Support

Authors
Lee, Young-GeunJung, Han-SamChung, Ki-Seok
Issue Date
Jul-2009
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Keywords
digital arithmetic; digital signal processors; constant multiplication; power consumption
Citation
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E92A, no.7, pp.1623 - 1632
Indexed
SCIE
SCOPUS
Journal Title
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
Volume
E92A
Number
7
Start Page
1623
End Page
1632
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/176561
DOI
10.1587/transfun.E92.A.1623
ISSN
1745-1337
Abstract
Many DSP applications such as FIR filtering and DCT (discrete cosine transformation) require multiplication with constants. Therefore, optimizing the performance of constant multiplication improves the overall performance of these applications. It is well-known that shifting can replace a constant multiplication if the constant is a power of two. In this paper, we extend this idea in such a way that by employing more than two barrel shifters, we can design highly efficient constant multipliers, We have found that by using two or three shifters, we can generate a large set of constants. Using these constants, we can execute a typical set of FIR or DCT applications with few errors. Furthermore, with variable precision support, we can carry Out a fairly large class of DSP applications with high computational efficiency. Compared to conventional multipliers, we can achieve power savings of up to 56% with negligible computational errors.
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COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)
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