An incremental floorplanning algorithm for temperature reduction
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Won Jin | - |
dc.contributor.author | Chung, Ki Seok | - |
dc.date.accessioned | 2022-12-21T06:23:32Z | - |
dc.date.available | 2022-12-21T06:23:32Z | - |
dc.date.created | 2022-09-16 | - |
dc.date.issued | 2007-09 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/179571 | - |
dc.description.abstract | Integrating a large number of transistors in a limited silicon area causes chip temperature to increase rapidly. High temperature incurs a number of design problems such as high leakage power consumption and unreliable operations. It is worthwhile to note that the peak temperature of a chip may go down by finding an optimal floorplanning. Especially, it is very important to consider temporal correlation of temperature states because the temperature of a block may go up or down depending on the temperatures of the surrounding blocks. In this paper, we propose a set of floorplanning techniques to reduce the peak temperature. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | An incremental floorplanning algorithm for temperature reduction | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Chung, Ki Seok | - |
dc.identifier.doi | 10.1109/SOCC.2007.4545428 | - |
dc.identifier.scopusid | 2-s2.0-51049119195 | - |
dc.identifier.bibliographicCitation | Proceedings - 20th Anniversary IEEE International SOC Conference, pp.67 - 70 | - |
dc.relation.isPartOf | Proceedings - 20th Anniversary IEEE International SOC Conference | - |
dc.citation.title | Proceedings - 20th Anniversary IEEE International SOC Conference | - |
dc.citation.startPage | 67 | - |
dc.citation.endPage | 70 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | CMOS integrated circuits | - |
dc.subject.keywordPlus | Silicon | - |
dc.subject.keywordPlus | Floor-planning | - |
dc.subject.keywordPlus | Peak temperatures | - |
dc.subject.keywordPlus | High temperature operations | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/4545428 | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
222, Wangsimni-ro, Seongdong-gu, Seoul, 04763, Korea+82-2-2220-1365
COPYRIGHT © 2021 HANYANG UNIVERSITY.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.