An incremental floorplanning algorithm for temperature reduction
- Authors
- Kim, Won Jin; Chung, Ki Seok
- Issue Date
- Sep-2007
- Publisher
- IEEE
- Citation
- Proceedings - 20th Anniversary IEEE International SOC Conference, pp.67 - 70
- Indexed
- SCOPUS
- Journal Title
- Proceedings - 20th Anniversary IEEE International SOC Conference
- Start Page
- 67
- End Page
- 70
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/179571
- DOI
- 10.1109/SOCC.2007.4545428
- ISSN
- 0000-0000
- Abstract
- Integrating a large number of transistors in a limited silicon area causes chip temperature to increase rapidly. High temperature incurs a number of design problems such as high leakage power consumption and unreliable operations. It is worthwhile to note that the peak temperature of a chip may go down by finding an optimal floorplanning. Especially, it is very important to consider temporal correlation of temperature states because the temperature of a block may go up or down depending on the temperatures of the surrounding blocks. In this paper, we propose a set of floorplanning techniques to reduce the peak temperature.
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