Investigation of Tunneling Current in SiO2/HfO2 Gate Stacks for Flash Memory Applications
- Authors
- Chakrabarti, Bhaswar; Kang, Heesoo; Brennan, Barry; Park, Tae Joo; Cantley, Kurtis D.; Pirkle, Adam; McDonnell, Stephen; Kim, Jiyoung; Wallace, Robert M.; Vogel, Eric M.
- Issue Date
- Dec-2011
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Charge traps; Fowler-Nordheim (F-N) tunneling; high-k dielectric; tunnel barrier engineering
- Citation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, v.58, no.12, pp.4189 - 4195
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON ELECTRON DEVICES
- Volume
- 58
- Number
- 12
- Start Page
- 4189
- End Page
- 4195
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/181992
- DOI
- 10.1109/TED.2011.2170198
- ISSN
- 0018-9383
- Abstract
- Despite theoretical predictions of significant performance improvement in Flash memory devices using tunnel-barrier-engineered (TBE) structures, there have been very few reports that demonstrate experimental verification. In this work, we have studied the role of factors such as high-k layer thickness and annealing recipe on the performance of SiO2/HfO2 gate stacks by electrical and physical characterization techniques. Results indicate that thick HfO2 is not suitable for use in SiO2/HfO2 stacks for tunnel barrier engineering applications. The performance of SiO2/HfO2 stacks improves with decreasing thickness of the HfO2 layer. Mild (10%) O-2/N-2 anneals do not significantly affect performance, although annealing above 600 degrees C resulted in a slight decrease in the program current. Based on our observations, we propose a method to improve the program current in these structures and a simple hypothesis for the physical model for tunneling in SiO2/HfO2 stacks.
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