A High-Frequency and Low-Jitter DLL with Quadrature Error and Duty Cycle Corrections Based on Asynchronous Sampling
- Authors
- Park, Gijin; Lee, Dongjun; Han, Jaeduk; Bae, Woorham
- Issue Date
- Feb-2023
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Clocks; Jitter; Detectors; Delay lines; Calibration; Frequency measurement; Phase measurement; Clock generation; delay-locked loops (DLLs); duty-cycle error correction; multiphase clock; quadrature error correction
- Citation
- IEEE SOLID-STATE CIRCUITS LETTERS, v.6, pp.41 - 44
- Indexed
- SCOPUS
- Journal Title
- IEEE SOLID-STATE CIRCUITS LETTERS
- Volume
- 6
- Start Page
- 41
- End Page
- 44
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/184955
- DOI
- 10.1109/LSSC.2023.3242902
- Abstract
- This paper presents a quadrature error and duty-cycle correction circuit based on an asynchronous sampling technique. Sampling the multi-phased clocks provides their phase and duty-cycle information, which are then utilized to compensate for the quadrature and duty-cycle errors. The intrinsic down-conversion operation of the proposed sampling approach enhances the correction accuracy by mitigating circuit mismatch effects. The quadrature-error corrector (QEC) and duty-cycle corrector (DCC) circuits receive control signals generated from the asynchronous phase detectors and correct the clock outputs accordingly. Combined with a delay-locked loop (DLL), the proposed design is fabricated in a 40-nm CMOS process, consumes 7.2 mW, and occupies 0.023 mm. It achieves 0.837-ps RMS jitter and 1.68∘ maximum phase error from multiple chip samples.
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