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A 12-Gb/s Baud-rate Clock and Data Recovery with 75% Phase-detection Probability by Precoding and Integration-Hold-Reset Frontend

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dc.contributor.authorSeo, Hyeongmin-
dc.contributor.authorHan, Jiyun-
dc.contributor.authorKim, Kyungmin-
dc.contributor.authorLim, Baekjin-
dc.contributor.authorShin, Eunseok-
dc.contributor.authorChoi, Youngdon-
dc.contributor.authorKo, Hyungjong-
dc.contributor.authorChoi, Jung-Hwan-
dc.contributor.authorLee, Sang-Hyun-
dc.contributor.authorYoo, Changsik-
dc.contributor.authorHan, Jaeduk-
dc.date.accessioned2023-05-03T11:23:42Z-
dc.date.available2023-05-03T11:23:42Z-
dc.date.created2022-11-02-
dc.date.issued2023-02-
dc.identifier.issn1549-7747-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/185241-
dc.description.abstractThis paper describes a 12-Gb/s quarter-rate receiver with a current-integrating baud-rate clock and data recovery (CDR) technique. The proposed CDR receives a pre-encoded non-return-to-zero (NRZ) data stream and integrates with 0.5-UI phase offset to extract the phase information. By sampling three consecutive symbols with multiple thresholds in the proposed phase detector, the CDR achieves a 75% phase-detection probability, which is the highest among baud-rate CDRs and leads to a better tracking bandwidth and jitter tolerance. The 12-Gb/s baud-rate CDR prototype is implemented in a 28 nm CMOS process and consumes 77 mW from a 1.2-V supply.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA 12-Gb/s Baud-rate Clock and Data Recovery with 75% Phase-detection Probability by Precoding and Integration-Hold-Reset Frontend-
dc.typeArticle-
dc.contributor.affiliatedAuthorHan, Jaeduk-
dc.identifier.doi10.1109/TCSII.2022.3212881-
dc.identifier.scopusid2-s2.0-85139821792-
dc.identifier.wosid000929815700012-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.70, no.2, pp.411 - 415-
dc.relation.isPartOfIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS-
dc.citation.titleIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS-
dc.citation.volume70-
dc.citation.number2-
dc.citation.startPage411-
dc.citation.endPage415-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusDFE-
dc.subject.keywordPlusCDR-
dc.subject.keywordAuthorClocks-
dc.subject.keywordAuthorSymbols-
dc.subject.keywordAuthorReceivers-
dc.subject.keywordAuthorTiming-
dc.subject.keywordAuthorPhase detection-
dc.subject.keywordAuthorJitter-
dc.subject.keywordAuthorPrecoding-
dc.subject.keywordAuthorBaud-rate CDR-
dc.subject.keywordAuthorcurrent integration-
dc.subject.keywordAuthortransition probability-
dc.subject.keywordAuthorreceiver-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/9913680-
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