A 12-Gb/s Baud-rate Clock and Data Recovery with 75% Phase-detection Probability by Precoding and Integration-Hold-Reset Frontend
- Authors
- Seo, Hyeongmin; Han, Jiyun; Kim, Kyungmin; Lim, Baekjin; Shin, Eunseok; Choi, Youngdon; Ko, Hyungjong; Choi, Jung-Hwan; Lee, Sang-Hyun; Yoo, Changsik; Han, Jaeduk
- Issue Date
- Feb-2023
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Clocks; Symbols; Receivers; Timing; Phase detection; Jitter; Precoding; Baud-rate CDR; current integration; transition probability; receiver
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.70, no.2, pp.411 - 415
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 70
- Number
- 2
- Start Page
- 411
- End Page
- 415
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/185241
- DOI
- 10.1109/TCSII.2022.3212881
- ISSN
- 1549-7747
- Abstract
- This paper describes a 12-Gb/s quarter-rate receiver with a current-integrating baud-rate clock and data recovery (CDR) technique. The proposed CDR receives a pre-encoded non-return-to-zero (NRZ) data stream and integrates with 0.5-UI phase offset to extract the phase information. By sampling three consecutive symbols with multiple thresholds in the proposed phase detector, the CDR achieves a 75% phase-detection probability, which is the highest among baud-rate CDRs and leads to a better tracking bandwidth and jitter tolerance. The 12-Gb/s baud-rate CDR prototype is implemented in a 28 nm CMOS process and consumes 77 mW from a 1.2-V supply.
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