6.8 A 100Gb/s 1.6VppdPAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm
- Authors
- Yang, Jeonghyu; Song, Eunji; Hong, Seungwook; Lee, Dongjun; Lee, Sangwan; Im, Hyunwoo; Shin, Taeho; Han, Jaeduk
- Issue Date
- Feb-2023
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Citation
- Digest of Technical Papers - IEEE International Solid-State Circuits Conference, v.2023-February, pp.122 - 124
- Indexed
- SCOPUS
- Journal Title
- Digest of Technical Papers - IEEE International Solid-State Circuits Conference
- Volume
- 2023-February
- Start Page
- 122
- End Page
- 124
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/186014
- DOI
- 10.1109/ISSCC42615.2023.10067452
- ISSN
- 0193-6530
- Abstract
- To match pace with the performance enhancement of computing systems for data-centric applications, data rates of high-speed I/O transceivers for the computing systems are increasing beyond 100Gb/s/lane. Four-level pulse-amplitude modulation (PAM-4) signaling has been widely adopted due to its energy efficiency and high data rate under finite channel bandwidth [1-4]. To overcome the timing constraints related to the dynamic power consumption and horizontal eye margin, transmitters with higher modulation complexities such as PAM-8 are required for next-generation wireline communication systems. However, as observed in previous PAM-4 transmitter designs, multi-level signaling schemes suffer from their limited signal-to-noise ratios (SNR) and increased bit-error ratios (BER), as the dynamic range is divided down due to maximum swing constraints. To achieve a high data rate (100Gb/s/lane) without sacrificing the eye-margin performance, this paper presents a reconfigurable high-swing current-mode transmitter with hybrid FFE tap configurations and high-speed frontend serializers in 40nm CMOS technology. © 2023 IEEE.
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