A Simple Timing-skew Calibration using Flip-flops for Time-interleaved ADCs
- Authors
- Lim, Ji-Hun; Park, Sang-Gyu
- Issue Date
- Apr-2023
- Publisher
- IEEK PUBLICATION CENTER
- Keywords
- ime-interleaved; SAR ADC; timing-skew calibration
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.23, no.2, pp.89 - 97
- Indexed
- SCIE
SCOPUS
KCI
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 23
- Number
- 2
- Start Page
- 89
- End Page
- 97
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/186346
- DOI
- 10.5573/JSTS.2023.23.2.89
- ISSN
- 1598-1657
- Abstract
- paper presents a simple timing-skew calibration circuit for time-interleaved ADCs. At the core of the skew calibration scheme lies a pair of D flip-flops to detect the sign of the relative timing between a channel clock and the reference clocks. The D flip-flops form a latch structure to detect the sign of timing skew. The detected sign of the timing skew is accumulated by counters and used to control shuntcapacitor-inverter variable delay lines to adjust the timing of the channel clocks. Although this scheme cannot remove the skew from mismatches after the timing comparison point, it should be able to reduce the bulk of the timing skew. The performance of the calibration circuit implemented using a 28 nm CMOS technology was verified by post-layout simulations.
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