Design of a Low-Power and Area-Efficient LDO Regulator using a Negative-R Assisted Technique
- Authors
- Kim, Jung Sik; Javed, Khurram; Roh, Jeongjin
- Issue Date
- Jun-2023
- Publisher
- Institute of Electrical and Electronics Engineers
- Keywords
- area-efficient; Gain; low dropout (LDO) regulator; low-power; Mathematical models; negative-R-assisted LDO; power management IC (PMIC); Regulation; Regulators; Resistance; Transconductance; Transistors
- Citation
- IEEE Transactions on Circuits and Systems II: Express Briefs, pp.1 - 5
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Transactions on Circuits and Systems II: Express Briefs
- Start Page
- 1
- End Page
- 5
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/187387
- DOI
- 10.1109/TCSII.2023.3289497
- ISSN
- 1549-7747
- Abstract
- To mitigate the non-ideal virtual ground at the feedback node of a low dropout (LDO) regulator, this brief presents an LDO with an off-chip capacitor that uses a negative-R assisted technique, which enhances its performance, including load/line regulation and power supply rejection (PSR). This technique enables the LDO to achieve improved performance despite the small size of the pass transistor, resulting in low-power and area-efficient LDO regulators. The proposed negative-R-assisted LDO provides 100 mA, with load regulation of 0.09 mV/mA, line regulation of 6 mV/V, and PSR of -31 dB. The proposed negative-R-assisted LDO was implemented with 150 nm transistors in a 28 nm standard CMOS process with an active area of 4,200 μm2. The proposed LDO achieves a superior figure-of-merit (FoM) of 13.5 ps (FoM1) and 0.057 ps∙mm2 (FoM2). IEEE
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