Comprehensive TCAD-Based Validation of Interface Trap-Assisted Ferroelectric Polarization in Ferroelectric-Gate Field-Effect Transistor Memory
- Authors
- Lee, Kitae; Kim, Sihyun; Kim, Munhyeon; Lee, Jong-Ho; Kwon, Daewoong; Park, Byung-Gook
- Issue Date
- Mar-2022
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Iron; FeFETs; Tunneling; Capacitors; Logic gates; Tin; Electron traps; Ferroelectric; ferroelectric-gate field-effect transistor (FeFET); interface trap; memory; polarization; technology computer-aided design (TCAD)
- Citation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, v.69, no.3, pp.1048 - 1053
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON ELECTRON DEVICES
- Volume
- 69
- Number
- 3
- Start Page
- 1048
- End Page
- 1053
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/188665
- DOI
- 10.1109/TED.2022.3144965
- ISSN
- 0018-9383
- Abstract
- In this article, the interface trap-assisted ferroelectric polarization in ferroelectric-gate field effect transistors (FeFETs) is investigated based on technology computer-aided design (TCAD) simulations. The metal-ferroelectric-metal (MFM) capacitors and FeFETs are fabricated to reflect ferroelectric and device model parameters to the simulations. By introducing interface traps between ferroelectric layer and Interlayer (FE/IL) and implementing the charge trapping through nonlocal tunneling model, it is revealed that the trapped charges at the FE/IL interface enhance the polarization of the FE, and they determine a memory window (MW) by the compensation between the polarization enhancement and the trapping-induced threshold voltage shift. Furthermore, the effects of the remaining trapped charges depending on a trap relaxation on the MW are rigorously analyzed by monitoring the transient changes of the polarization and the trapped charges in pulse program/read operations.
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