Ferroelectric-Gate Field-Effect Transistor Memory With Recessed Channel
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Kitae | - |
dc.contributor.author | Bae, Jong-Ho | - |
dc.contributor.author | Kim, Sihyun | - |
dc.contributor.author | Lee, Jong-Ho | - |
dc.contributor.author | Park, Byung-Gook | - |
dc.contributor.author | Kwon, Daewoong | - |
dc.date.accessioned | 2023-09-04T19:10:39Z | - |
dc.date.available | 2023-09-04T19:10:39Z | - |
dc.date.created | 2023-07-19 | - |
dc.date.issued | 2020-08 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/190135 | - |
dc.description.abstract | We demonstrate a novel ferroelectric-gate field effect transistor with recessed channel (R-FeFET) to improve memory window (MW), program/erase speed, long-time retention, and endurance simultaneously. Based on technology computer-aided design (TCAD) simulations including calibrated ferroelectric material (FE) parameters, it is revealed that the polarization is enhanced by the larger electric field (e-field) across the FE compared to a conventional planar FeFET, resulting in the wider MW and the faster program/erase speed. Moreover, the endurance/retention of the R-FeFET is expected to be improved as the e-field across the SiO2 interlayer is significantly reduced. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Ferroelectric-Gate Field-Effect Transistor Memory With Recessed Channel | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kwon, Daewoong | - |
dc.identifier.doi | 10.1109/LED.2020.3001129 | - |
dc.identifier.scopusid | 2-s2.0-85089482233 | - |
dc.identifier.wosid | 000552970000013 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.41, no.8, pp.1201 - 1204 | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 41 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 1201 | - |
dc.citation.endPage | 1204 | - |
dc.type.rims | ART | - |
dc.type.docType | 정기 학술지(letter(letters to the editor)) | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | TRANSIENT NEGATIVE CAPACITANCE | - |
dc.subject.keywordPlus | FET | - |
dc.subject.keywordAuthor | FeFET endurance | - |
dc.subject.keywordAuthor | FeFET program/erase speed | - |
dc.subject.keywordAuthor | ferroelectric-gate FET (FeFET) | - |
dc.subject.keywordAuthor | Recessed channel | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9112263 | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
222, Wangsimni-ro, Seongdong-gu, Seoul, 04763, Korea+82-2-2220-1365
COPYRIGHT © 2021 HANYANG UNIVERSITY.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.