Detailed Information

Cited 0 time in webofscience Cited 0 time in scopus
Metadata Downloads

Ferroelectric-Gate Field-Effect Transistor Memory With Recessed Channel

Full metadata record
DC Field Value Language
dc.contributor.authorLee, Kitae-
dc.contributor.authorBae, Jong-Ho-
dc.contributor.authorKim, Sihyun-
dc.contributor.authorLee, Jong-Ho-
dc.contributor.authorPark, Byung-Gook-
dc.contributor.authorKwon, Daewoong-
dc.date.accessioned2023-09-04T19:10:39Z-
dc.date.available2023-09-04T19:10:39Z-
dc.date.created2023-07-19-
dc.date.issued2020-08-
dc.identifier.issn0741-3106-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/190135-
dc.description.abstractWe demonstrate a novel ferroelectric-gate field effect transistor with recessed channel (R-FeFET) to improve memory window (MW), program/erase speed, long-time retention, and endurance simultaneously. Based on technology computer-aided design (TCAD) simulations including calibrated ferroelectric material (FE) parameters, it is revealed that the polarization is enhanced by the larger electric field (e-field) across the FE compared to a conventional planar FeFET, resulting in the wider MW and the faster program/erase speed. Moreover, the endurance/retention of the R-FeFET is expected to be improved as the e-field across the SiO2 interlayer is significantly reduced.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleFerroelectric-Gate Field-Effect Transistor Memory With Recessed Channel-
dc.typeArticle-
dc.contributor.affiliatedAuthorKwon, Daewoong-
dc.identifier.doi10.1109/LED.2020.3001129-
dc.identifier.scopusid2-s2.0-85089482233-
dc.identifier.wosid000552970000013-
dc.identifier.bibliographicCitationIEEE ELECTRON DEVICE LETTERS, v.41, no.8, pp.1201 - 1204-
dc.relation.isPartOfIEEE ELECTRON DEVICE LETTERS-
dc.citation.titleIEEE ELECTRON DEVICE LETTERS-
dc.citation.volume41-
dc.citation.number8-
dc.citation.startPage1201-
dc.citation.endPage1204-
dc.type.rimsART-
dc.type.docType정기 학술지(letter(letters to the editor))-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusTRANSIENT NEGATIVE CAPACITANCE-
dc.subject.keywordPlusFET-
dc.subject.keywordAuthorFeFET endurance-
dc.subject.keywordAuthorFeFET program/erase speed-
dc.subject.keywordAuthorferroelectric-gate FET (FeFET)-
dc.subject.keywordAuthorRecessed channel-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/9112263-
Files in This Item
Go to Link
Appears in
Collections
서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles

qrcode

Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.

Related Researcher

Researcher Kwon, Daewoong photo

Kwon, Daewoong
COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)
Read more

Altmetrics

Total Views & Downloads

BROWSE