An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS

Abstract

A noise-immune spatial-delta coding (SDC) scheme is proposed for single-ended multi-lane links. The SDC technique allows differential sensing of single-ended PAM2 signals for high signal integrity while still achieving the same pin efficiency as the 8b9b data bus (DBI) scheme, providing high compatibility with conventional DDR interfaces. The SDC encoding/decoding functions are implemented with simple XOR gates to minimize power and latency overhead. Continuous-time linear equalizers in the receiver compensate for distortions in incoming pseudodifferential signals with high tolerance on dynamic common-mode switching associated with the SDC operation. An 8b9b SDC transceiver prototype array composed of nine data channels and a differential clock channel has been fabricated in 28-nm CMOS technology for demonstration. The transceiver array achieves a 77.44 Gb/s aggregate data rate with 9 wires at 9.68 Gbaud/s. The bit error rate is measured to be less than 1e-12 while consuming 4.9 pJ/b from a 1.25-V supply.