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A 50 ms/s First-Order Mismatch Error Shaping and Third-Order Noise-Shaping SAR ADC for IOT Applications
- Authors
- Jang, Jin-Yeop; Park, Sang-Gyu
- Issue Date
- Nov-2023
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- Hardware Reusing EF-CIFF Structure; Mismatch Error Shaping (MES); Noise-Shaped SAR ADC; Split Capacitor Array Digital to Analog Converter (DAC); Two-Level Digital Prediction
- Citation
- Proceedings of 2023 8th IEEE International Conference on Network Intelligence and Digital Content, IC-NIDC 2023, pp 481 - 485
- Pages
- 5
- Indexed
- SCOPUS
- Journal Title
- Proceedings of 2023 8th IEEE International Conference on Network Intelligence and Digital Content, IC-NIDC 2023
- Start Page
- 481
- End Page
- 485
- ISSN
- 2374-0272
2575-4955
- Abstract
- This article presents a first order Mismatch Error Shaping (MES) and third-order Noise Shaping (NS) Successive Approximation Register (SAR) analog to digital converter (ADC). We choose fully dynamic hardware reusing (HR) error feedback, cascade of integrators with feed forward (EF-CIFF) structure to reduce the power consumption, and to increase the sampling speed. In addition, to enhance the resolution, a MES scheme with two-level digital prediction is implemented to remove the distortion caused by the capacitive digital to analog converter (CDAC) mismatch. The SPICE level simulations of the proposed ADC implemented using a 28-nm CMOS process show 85 dB signal-to-noise-distortion ratio (SNDR) with 1.56 MHz bandwidth (oversampling ratio (OSR) = 16).
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Related Researcher
- Park, Sang Gyu
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)