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Multi-Phase Frequency Divider Generator with Process-Independent Automation

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dc.contributor.authorJang, Jihoon-
dc.contributor.authorJeong, Heedo-
dc.contributor.authorHan, Jaeduk-
dc.date.accessioned2024-11-28T13:31:35Z-
dc.date.available2024-11-28T13:31:35Z-
dc.date.issued2023-10-
dc.identifier.issn2163-9612-
dc.identifier.issn2472-9655-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/196663-
dc.description.abstractThis work presents an automatic circuit generator for multi-phase frequency dividers. The schematic and layout generator scripts are parameterized, allowing users to customize the number of output phases, the number of fingers, and the arrangement of the physical layout. It increases design flexibility, satisfying a wide range of user requirements and specifications. The proposed generator has been successfully validated by generating DRC-and-LVS clean physical layouts in both 40-nm and 28-nm CMOS processes.-
dc.format.extent2-
dc.language영어-
dc.language.isoENG-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleMulti-Phase Frequency Divider Generator with Process-Independent Automation-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/ISOCC59558.2023.10396246-
dc.identifier.scopusid2-s2.0-85184807946-
dc.identifier.wosid001169439300060-
dc.identifier.bibliographicCitationProceedings - International SoC Design Conference 2023, ISOCC 2023, pp 129 - 130-
dc.citation.titleProceedings - International SoC Design Conference 2023, ISOCC 2023-
dc.citation.startPage129-
dc.citation.endPage130-
dc.type.docTypeProceedings Paper-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusComputer aided design-
dc.subject.keywordPlusFrequency dividing circuits-
dc.subject.keywordPlusIntegrated circuit manufacture-
dc.subject.keywordPlusTiming circuits-
dc.subject.keywordAuthorautomation of circuit design-
dc.subject.keywordAuthorclock divider-
dc.subject.keywordAuthordesign automation-
dc.subject.keywordAuthorfrequency divider-
dc.subject.keywordAuthorLAYGO2-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/10396246-
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