Multi-Phase Frequency Divider Generator with Process-Independent Automation
- Authors
- Jang, Jihoon; Jeong, Heedo; Han, Jaeduk
- Issue Date
- Oct-2023
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- automation of circuit design; clock divider; design automation; frequency divider; LAYGO2
- Citation
- Proceedings - International SoC Design Conference 2023, ISOCC 2023, pp 129 - 130
- Pages
- 2
- Indexed
- SCOPUS
- Journal Title
- Proceedings - International SoC Design Conference 2023, ISOCC 2023
- Start Page
- 129
- End Page
- 130
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/196663
- DOI
- 10.1109/ISOCC59558.2023.10396246
- ISSN
- 2163-9612
2472-9655
- Abstract
- This work presents an automatic circuit generator for multi-phase frequency dividers. The schematic and layout generator scripts are parameterized, allowing users to customize the number of output phases, the number of fingers, and the arrangement of the physical layout. It increases design flexibility, satisfying a wide range of user requirements and specifications. The proposed generator has been successfully validated by generating DRC-and-LVS clean physical layouts in both 40-nm and 28-nm CMOS processes.
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Collections - 서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles

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