Row hammer-induced D0 failure improvement in sub-20 nm DRAM using an air gap

Abstract

As the density of bit cells increases, reliability issues in state-of-the-art dynamic random access memory (DRAM) become critical. Row hammer (RH) is a reliability issue in sub-20 nm DRAM products. This work proposes an air gap technique (i.e. placing an air gap beneath the passing wordline (PWL)), to suppress the RH in sub-20 nm DRAM. Using 3D TCAD simulations, the electric field and Shockley-Read-Hall recombination rate are investigated when the PWL is activated. When the PWL is deactivated, the leakage current towards the bitline is extracted to investigate the impact of the air gap on RH. It turns out that a low-k dielectric material in the air gap can effectively help to reduce the electric field intensity near the interface between shallow-trench-isolation (STI) and silicon. A relatively weak electric field can prevent the flow of electrons that causes read/write errors through trap-assisted recombination. By adopting the air gap in STI, an 82% improvement was estimated in terms of alleviating RH.