Reliability Engineering of High-Mobility IGZO Transistors via Gate Insulator Heterostructures Grown by Atomic Layer Deposition

Abstract

The reliability of oxide-semiconductor (OS) thin-film transistors (TFTs) is significantly influenced by the gate insulator (GI). During electrical bias stress, the defect sites near the semiconductor/GI interface and/or within the GI may trap electrons, which makes the threshold voltage (Vth) shift toward positive values. On the other hand, carbon (C) or hydrogen (H) atoms may diffuse from the GI into the active layer, and act as shallow donors, which induce negative Vth shifts (Delta Vth). In this paper, an in situ atomic layer deposition (ALD)-based GI heterostructure is introduced, which consists of a stack of two complementary materials, namely Al2O3 and SiO2. Here, a competition occurs between electron trapping in Al2O3 (positive Delta Vth) and carrier generation from H atoms in SiO2 (negative Delta Vth) which allows the achievement of nearly zero Delta Vth under positive bias temperature stress (PBTS). This strategy is successfully applied to a high-mobility (>50 cm(2) Vs(-1)) ALD-based indium-gallium-zinc oxide (IGZO) device, resulting in a net increment Vth of -0.02 V under PBTS and drain current variation (Delta I-D) of +0.49% under constant current stress (CCS). The application of an in situ ALD process thus offers valuable insights to resolve the mobility versus reliability trade-off in high-performance oxide TFTs.

The reliability of oxide-semiconductor (OS) thin-film transistors (TFTs) is significantly influenced by the gate insulator (GI). During electrical bias stress, the defect sites near the semiconductor/GI interface and/or within the GI may trap electrons, which makes the threshold voltage (Vth) shift toward positive values. On the other hand, carbon (C) or hydrogen (H) atoms may diffuse from the GI into the active layer, and act as shallow donors, which induce negative Vth shifts (Vth). In this paper, an in situ atomic layer deposition (ALD)-based GI heterostructure is introduced, which consists of a stack of two complementary materials, namely Al2O3 and SiO2. Here, a competition occurs between electron trapping in Al2O3 (positive Vth) and carrier generation from H atoms in SiO2 (negative Vth) which allows the achievement of nearly zero Vth under positive bias temperature stress (PBTS). This strategy is successfully applied to a high-mobility (>50 cm2 Vs−1) ALD-based indium-gallium-zinc oxide (IGZO) device, resulting in a net ∆Vth of −0.02 V under PBTS and drain current variation (∆ID) of +0.49% under constant current stress (CCS). The application of an in situ ALD process thus offers valuable insights to resolve the mobility versus reliability trade-off in high-performance oxide TFTs.