CMOS Image Sensor 용 저전력 디지털 카운터

Abstract

In this paper, a new low-power counter for CMOS image sensor(CIS) using the digital correlated double sampling (digital CDS) is proposed. The power consumption of the proposed low-power counter can be reduced by 50% compared with the traditional counter by reducing toggling of the flip—flop for lease significant bit (LSB). The proposed low-power counter is simulated with a 0.11 «#m CMOS process. The simulation result shows that the power consumption of the proposed circuit at 300 MHz clock frequency is 3.53 #W which is 52.2% of that of the traditional counter.