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Dynamic Rate Neural Acceleration Using Multiprocessing Mode Support

Authors
Lee, InhoLee, YangkiUm, HongjunHong, SeongminPark, Yongjun
Issue Date
Oct-2022
Publisher
Institute of Electrical and Electronics Engineers Inc.
Keywords
Accelerator; approximation; neural networks; region of interest (ROI); weight quantization
Citation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.30, no.10, pp 1461 - 1472
Pages
12
Indexed
SCIE
SCOPUS
Journal Title
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume
30
Number
10
Start Page
1461
End Page
1472
URI
https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/203522
DOI
10.1109/TVLSI.2022.3178615
ISSN
1063-8210
1557-9999
Abstract
Multiobject detection has become an integral component in various neural applications, such as autonomous driving and augmented reality. The system should be able to recognize and process multiple objects simultaneously. Moreover, the performance requirements for this system can be dynamically changed depending on the number of regions of interest (ROIs) in each frame. Consequently, the processing unit (PU) of the neural acceleration system should provide various inference rates. Therefore, we present a field-programmable gate array (FPGA)-based dynamic rate neural acceleration system called MultiLockOn to dynamically change the inference performance according to the number of ROIs per frame. It supports multiprocessing modes with different speeds through the introduction of novel multi-mode processing engines (PEs) comprising minimum reconfigurable interconnections across inference modes to minimize hardware overhead. The MultiLockOn system can provide an improvement of up to 4<inline-formula> <tex-math notation=LaTeX>$\times$</tex-math> </inline-formula> in the inference performance compared to that of DNNWeaver and 5.7<inline-formula> <tex-math notation=LaTeX>$\times$</tex-math> </inline-formula> compared to that of the ARM Cortex-A53 with minimum accuracy loss by supporting the multiprocessing modes.
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