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Analysis of Test Environment Configuration for High-Speed Link Chip Measurement
- Authors
- Jo, Yunseong; Kim, Hyuntae; Han, Jaeduk
- Issue Date
- Aug-2024
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- characteristic impedance; impedance matching; Printed circuit board (PCB)
- Citation
- Proceedings - International SoC Design Conference 2024, ISOCC 2024, pp 430 - 431
- Pages
- 2
- Indexed
- SCOPUS
- Journal Title
- Proceedings - International SoC Design Conference 2024, ISOCC 2024
- Start Page
- 430
- End Page
- 431
- ISSN
- 2163-9612
- Abstract
- This paper presents an analysis of a test channel environment designed for high-speed serial links. The microstrip line channel was fabricated using a 4-layer FR-4. Using this environment, various components susceptible to impedance mismatching were fabricated to compare signal integrity. The bonding wire length, microstrip line width, and RF connector footprint were constructed, followed by measurements of the S-parameters and TDR impedance.
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Related Researcher
- Han, Jaeduk
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)