Vertically Stackable Memcapacitor Crossbar Array based on NAND Flash Array Structure

Abstract

In this work, a vertically stackable 4F2 memcapacitor crossbar array based on charge trap flash (CTF) is experimentally demonstrated with a TiN-Al2O3- Si3N4-SiO2-Si (TANOS) gate stack. 4-bit multi-level operation of the fabricated 24 × 48 array is verified with more than 10 years of retention and no read/write disturbance. Also, vector-matrix multiplication (VMM) operations with an error of 0.227 % are validated, along with read operations using a sensing circuit. Based on the measurement data of the planar array, the capability of performing read/write operations with a vertically stacked 3-D structure is verified through TCAD simulations. A weight transfer procedure is also provided to enhance VMM accuracy in a scaled-down vertical structure, resulting in significantly suppressed VMM errors.