A 32-to-50Gb/s/pin Single-Ended PAM-4 Transmitter with a ZQ-Based FFE and PAM-4 LSB DBI-DC Encoding

Abstract

With the rapid growth of the AI industry, demand for data processing and transmission has surged: highlighting the need for high-speed and energy-efficient data transmission between processors and memory. While data processing capabilities continue to advance, the memory-interface bandwidth has struggled to keep up; primarily limited by channel bandwidth and noise-susceptibility of single-ended signaling, which is commonly used for memory interfaces. One promising approach to overcome channel-bandwidth limitation is multi-level pulse amplitude modulation (PAMn), which increases the bit rate without increasing the baud rate, at the cost of increased (n) signaling levels. PAMn has been widely adopted for recent memory interfaces, such as PAM4 for GDDR6X [1,2] and PAM3 for GDDR7 [3,4]. However, the reduced signal-level spacing, 1/2 for PAM3 and 1/3 for PAM4, reduces the resulting signal-to-noise ratio (SNR). Therefore, implementing a high-bandwidth transmitter (TX) feed-forward equalizer (FFE) for PAMn is challenging. Furthermore, as PAMn signaling brings additional circuit complexity and power overhead; thus, a power-reduction data-bus encoding scheme, with minimal hardware overhead, is required.